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π Github λ§ν¬
https://github.com/heesik-kwon
βοΈ PROJECT
STM32 κ²μ νλ‘μ νΈ
HC-SR04 RTL μ€κ³ λ° κ²μ¦
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π AI μμ€ν
λ°λ체 μ€κ³
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GPIO μΆλ ₯
λΉνΈ μ°μ°κ³Ό λ§€ν¬λ‘ & GPIO μ
λ ₯ μ μ΄
UART & RS232ν΅μ
Interrupt μ μ΄
Timer
PWM μ μ΄
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Vivado μ¬μ©λ² & λ
Όλ¦¬κ²μ΄νΈ ꡬν
κ°μ°κΈ°
Clock Divider
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10000μ§ Counter
Moore FSM
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Stopwatch
Button Debounce
Watch & Stopwatch
RAM
UART
FIFO
HR-SC04 μ΄μν μΌμ
DHT11 μ¨μ΅λ μΌμ
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DUT
Verification Environment
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βοΈ Synopsis Custom Complier
Custom Compiler μ¬μ©λ² & NOT Gate
CMOS Schematic & Stick Diagram
Logic Gate Simulation - n input NAND Gate
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βοΈ AI μκ³ λ¦¬μ¦ κ΅¬μ‘°
Python κ°μ νκ²½ μ€μ & 리λ
μ€.VI λͺ
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OpenCV
Perceptron - Gate μκ°ν
Deep Learning
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Deep Learning
Raspberry Pi
βοΈ μ
무 λ©λͺ¨
- [ ] μμ§ μλλ‘ ν μΌ λ©λͺ¨
- [ ]
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π μ 곡 νμ΅
βοΈ λμ§νΈ λ
Όλ¦¬ νλ‘
Boolean Algebra and Logic Gates
Minterm/Maxterm & Various Logic Gates
Gate-Level Minimization
Combinational Logic and Binary Adder
Decimal Adder
Decimal Adder
Binary Multiplier & Magnitude Comparator
Decoder/Encoder & Multiplexer
Sequential Logic & Latch
Flip Flop
Sequential Logic Circuit μ€κ³(with. D . JK . T Flip Flop)
Sequential Logic Circuit Analysis
Moore & Mealy Machine
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