<aside> πŸ’‘

μ•ˆλ…•ν•˜μ„Έμš”. RTL 섀계 μ—”μ§€λ‹ˆμ–΄λ₯Ό λͺ©ν‘œλ‘œ 곡뢀 쀑인 κΆŒν¬μ‹μž…λ‹ˆλ‹€.

회둜 섀계가 κΆκΈˆν•˜μ‹  λΆ„λ“€, 그리고 μ €μ²˜λŸΌ μ—”μ§€λ‹ˆμ–΄λ‘œ μ„±μž₯ν•΄ λ‚˜κ°€λŠ” λΆ„λ“€κ»˜ 도움이 λ˜λŠ” λΈ”λ‘œκ·Έκ°€ 되길 λ°”λžλ‹ˆλ‹€ :)

</aside>

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πŸ”— Github 링크

https://github.com/heesik-kwon

βœ”οΈ PROJECT

STM32 κ²Œμž„ ν”„λ‘œμ νŠΈ

HC-SR04 RTL 섀계 및 검증

슀마트 냉μž₯κ³ (?)


πŸ“š AI μ‹œμŠ€ν…œ λ°˜λ„μ²΄ 섀계

βœ”οΈ ARM Architecture

GPIO 좜λ ₯

λΉ„νŠΈ μ—°μ‚°κ³Ό 맀크둜 & GPIO μž…λ ₯ μ œμ–΄

UART & RS232톡신

Interrupt μ œμ–΄

Timer

PWM μ œμ–΄

βœ”οΈ Verilog

Vivado μ‚¬μš©λ²• & λ…Όλ¦¬κ²Œμ΄νŠΈ κ΅¬ν˜„

κ°€μ‚°κΈ°

Clock Divider

FND Controller

10000μ§„ Counter

Moore FSM

Mealy FSM

Stopwatch

Button Debounce

Watch & Stopwatch

RAM

UART

FIFO

HR-SC04 초음파 μ„Όμ„œ

DHT11 μ˜¨μŠ΅λ„ μ„Όμ„œ

βœ”οΈ System Verilog

DUT

Verification Environment

Language Basic

Concurrency

Class

Randomization

Class Inheritance

Inter Thread Communication

Functional Coverage

βœ”οΈ Synopsis Custom Complier

Custom Compiler μ‚¬μš©λ²• & NOT Gate

CMOS Schematic & Stick Diagram

Logic Gate Simulation - n input NAND Gate

Logic Gate Simulation - n input NOR Gate

βœ”οΈ AI μ•Œκ³ λ¦¬μ¦˜ ꡬ쑰

Python 가상 ν™˜κ²½ μ„€μ • & λ¦¬λˆ…μŠ€.VI λͺ…λ Ήμ–΄

OpenCV

Perceptron - Gate μ‹œκ°ν™”

Deep Learning

μ„ ν˜• λͺ¨λΈ

Deep Learning

Raspberry Pi

βœ”οΈ 업무 λ©”λͺ¨


πŸ“š 전곡 ν•™μŠ΅

βœ”οΈ λ””μ§€ν„Έ 논리 회둜

Boolean Algebra and Logic Gates

Minterm/Maxterm & Various Logic Gates

Gate-Level Minimization

Combinational Logic and Binary Adder

Decimal Adder

Decimal Adder

Binary Multiplier & Magnitude Comparator

Decoder/Encoder & Multiplexer

Sequential Logic & Latch

Flip Flop

Sequential Logic Circuit 섀계(with. D . JK . T Flip Flop)

Sequential Logic Circuit Analysis

Moore & Mealy Machine

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