Responsibilities and Opportunities

• Memory BIST: BIRA/BIST insertion & simulation
• Logic Scan: Scan(compressor) insertion & DFT simulation, SoC DFT Planning
• DFD: scandump & scan to dram logic implementation
• Implement the physical design(RTL to GDS) to achieve the best PPA
• Support DSPs and/or contractors to do their best within the target TAT
• Propose architectural changes to enhance the final QoR

Key Qualifications

• Minimum of 8 years of experience with EDA tool workflows in a semiconductor environment
• Bachelor's or higher degree in Electrical Engineering or equivalent practical experience
• Proficiency in scripting languages such as Python, Tcl, or Perl for workflow automation and data visualization
• Experience in physical design processes and tools for automating RTL to Global Distribution System(GDS) workflows
• Experience in building RTL to GDS workflows
• Experience leading one or more aspects of physical design
• Experience in extracting of design parameters, Quality of Results(QoR), and analyzing trends