Responsibilities and opportunities

• Floorplanning/Powerplanning
• Placement, CTS(clock-tree synthesis) w/ or w/o H-tree
• Routing, DRC/DFM Fix, Static IR-drop, Dynamic IR-drop
• EM(Electro-Migration), DRC/DFM/LVS check, PERC check, GDS delivery
• Implement the physical design(RTL to GDS) to achieve the best PPA
• Support DSPs and/or contractors to do their best within the target TAT
• Propose architectural changes to enhance the final QoR

Key Qualifications

• Minimum of 8 years of experience with EDA tool workflows in a semiconductor environment
• Bachelor's or higher degree in Electrical Engineering or equivalent practical experience
• Experience in scripting(e.g., Python, Tcl, or Perl) for workflow automation and data visualization
• Experience in physical design processes and tools to automate RTL to Global Distribution System(GDS) workflows
• Experience in building RTL to GDS workflows
• Experience leading one or more aspects of physical design
• Experience in extraction of design parameters, Quality of Results(QoR), and analyzing trends