counter1.v

`timescale 1ns/10ps;

module counter1 (
    input clk, rst,
    output [3:0] cnt,
    output reg ind_cnt
);

reg [3:0] count;
assign cnt = count;

always @(posedge clk or posedge rst) begin
    if (rst) begin
        count <= 4'b0;
    end
    else begin
        count <= count + 4'b1;
    end
end

//reg ind_cnt;
always @(posedge clk or posedge rst) begin
    if (rst) begin
        ind_cnt <= 1'b0;
    end
    else if (count == 4'b1010) begin
        ind_cnt <= 1'b1;
    end
    else begin
        ind_cnt <= 1'b0;
    end
end

endmodule

counter1_xpro.v

`timescale 1ns/10ps

module counter1_xpro (
    input clk, rst,
    output [3:0] cnt,
    output ind_cnt
);

reg [3:0] count;
assign cnt = count;

//always @(posedge clk or posedge rst) begin
always @(posedge clk) begin
    //if (rst) begin
    //    count <= 4'b0;
    //end
    if (count == 4'd15)
        count <= 0;
    else
        count <= count + 4'b1;
end

reg ind_cnt;
always @(posedge clk or posedge rst) begin
    if (rst) begin
        ind_cnt <= 1'b0;
    end
    else if (count == 4'b1010)
        ind_cnt <= 1'b1;
    else
        ind_cnt <= 1'b0;
end

endmodule

tb_cnt.v

//`timescale 1ns/1ps

module tb_cnt();

reg clk, rst;
wire [3:0] cnt1, cnt2, cnt3_1, cnt3_2;

initial begin
	clk <= 1'b1;
	rst <= 1'b0;
	#5
	rst <= 1'b1;
	#5
	rst <= 1'b0;
	#400
	$finish;
end

counter1 TEST1(clk, rst, cnt1, ind_cnt1);
counter1_xpro TEST1_xpro(clk, rst, cnt1_xpro, ind_cnt1_xpro);
counter2 TEST2(clk, rst, cnt2);
counter3 TEST3(clk, rst, cnt3_1, cnt3_2);

always #5 clk <= ~clk;

endmodule

rtl sim

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