Aim: To implement Linear Feedback Shift Register (LFSR) using Verilog HDL; validate through simulation; analyze RTL schematic; and study FPGA register and logic utilization.

Apparatus Required: Xilinx Vivado

Theory:

A Linear Feedback Shift Register (LFSR) is a sequential circuit made of D flip-flops where:

• Data shifts from one flip-flop to another every clock cycle
• The input to the first flip-flop is a linear function (XOR) of selected outputs (called taps)

Characteristic polynomial of LFSR • n = of FFs = degree of polynomial • XOR feedback connection to FF i ⇔ coefficient of xi

coefficient = 0 if no connection coefficient = 1 if connection coefficients always included in characteristic polynomial: • x ^n (degree of polynomial & primary feedback) • x^0 = 1 (principle input to shift register) • Note: state of the LFSR ⇔ polynomial of degree n-1 • Example: P(x) = x3 + x + 1

Code:

module lfsr_3bit (
    input clk,
    input reset,
    output reg Qa, Qb, Qc
);

    wire Da, Db, Dc;

    // Galois Logic
    assign Da = Qc;
    assign Db = Qa ^ Qc;
    assign Dc = Qb;

    // Flip-Flops with custom reset
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            Qa <= 1'b0;
            Qb <= 1'b0;
            Qc <= 1'b1;   // ✅ non-zero initial state
        end else begin
            Qa <= Da;
            Qb <= Db;
            Qc <= Dc;
        end
    end

endmodule

`timescale 1ns/1ps

module tb_lfsr;

    reg clk, reset;
    wire Qa, Qb, Qc;

    lfsr_3bit uut (clk, reset, Qa, Qb, Qc);

    always #5 clk = ~clk;

    initial begin
        clk = 0;
        reset = 1;
        #10 reset = 0;

        $monitor("Time=%0t | %b%b%b", $time, Qa, Qb, Qc);

        #100 $finish;
    end

endmodule

Conclusion

In this experiment, a 3-bit Linear Feedback Shift Register (LFSR) was successfully implemented using Verilog HDL and validated through simulation in Xilinx Vivado.