Power Struggles: Revisiting the RISC vs. CISC Debate on Contemporary ARM and x86 Architectures

Comments

• Novel Idea

  • I want to see the RISC-oriented micro-archi perforamance VS. CISC-oriented micro-archi performance in x86.
    • RISC-orientend micro-arch : macro-op to micro-op ratio is around 1.
    • SHRINK said that many x86 instructions are not used because compiler does not produce them.

• Questions

  • decoding logic should be included in the ISA part
    • Even though ways of decoding the CISC-ISA is determined by micro-arch, they don’t even have to make such determination if it was RISC.

• Critique

  • They did not exclude the active(workload-dependent) main memory and I/O power.

  This methodology allows us to eliminate the main memory and I/O power and examine only processor power

  • code is RISC-like. And micro-archi overcomes the penelty (?)
    • x86 micro-op to macro-op ratio is less than 1.3 → gcc picks the RISC-like ISA.
    • the paper doesn’t test the “CISC-heavy compiler” for x86.
      • so we can’t know neither the power of CISC-oriented micro-architectural optimization nor the penalty of having CISC-heavy micro-architectural components.
      • in the intel micro-archi, there might be a possibility that only RISC-oriented part of micro-architecture is touched.

• Impact

  • CISC is specialization. RISC is generalization. But, in recent year, hardwares are built under the specialization target.
    • Also, code density is slightly higher for CISC.
    • TPU, tensor cores are CISC-like even only for the front-end

Intro

• previous work
  • RISC had a fundamental ISA benefits and CISC spent a lot for micro-architecture optimization to overcome its shortcomings

Information

ISA vs micro-architecture

They analyze multiple layers of metrics and classify them implicitly: The authors draw a clean ISA–microarchitecture boundary by defining the ISA strictly as the architectural contract visible to software and treating everything that happens after decode as microarchitecture.

ISA-related metrics

• Instruction count
• Instruction mix
• x86 macro-instruction vs µop expansion
• Code density effects

These are things the ISA could plausibly influence.

Microarchitecture-related metrics

• CPI
• Cache miss rates
• Branch mispredictions
• Memory-level parallelism
• Frequency scaling
• Power draw at a given performance point

When large performance differences appear without corresponding differences in ISA-level metrics, the authors attribute them to microarchitecture.

So they ask:

If we control for microarchitecture, does the ISA itself still cause performance gaps?

They do in-order vs in-order and out-of-order vs out-of-order comparisons:

• ARM Cortex-A8 ↔ Intel Atom (both in-order)
• ARM Cortex-A9 ↔ Intel Core i7 (both OoO)

This removes the common fallacy:

“ARM is efficient because it’s RISC”

when the real reason might be:

“ARM is efficient because it’s simpler / in-order / lower frequency”

Step 2: Attribute metrics to ISA-visible vs microarchitectural causes

They analyze multiple layers of metrics and classify them implicitly:

ISA-related metrics

• Instruction count
• Instruction mix
• x86 macro-instruction vs µop expansion
• Code density effects

These are things the ISA could plausibly influence.

Microarchitecture-related metrics

• CPI
• Cache miss rates
• Branch mispredictions
• Memory-level parallelism
• Frequency scaling
• Power draw at a given performance point

When large performance differences appear without corresponding differences in ISA-level metrics, the authors attribute them to microarchitecture.

Power

• ARM : 1-2W
• x86 : 5-36W