The original PlayStation.
Released on 03/12/1994 in Japan, 09/09/1995 in North America, 29/09/1995 in Europe.
A quick introduction
Sony knew that 3D hardware can get very messy to develop for. Thus, their debuting console will keep its design simple and practical… Although this may come with a cost!
CPU
The main processor is one of those ‘x designed by y, based on z and second-sourced from w’ which is a bit dense to summarise in a few sentences, so why don’t we start with some historical context?
The offering
The resulting CPU core runs at 33.87 MHz and features:
- The MIPS I ISA: The first version of the MIPS instruction set. Among many things, words are 32-bit long and the instruction set includes multiplication and division instructions.
- 32 general-purpose registers and 2 multiplication/division registers: These are 32-bit as well. One general-purpose register is always zero (R0), which is common in RISC processors.
- 32-bit data bus: In the PS1, the data bus forks into two buses.
- Main Bus (32-bit) → Connects to main RAM, the MDEC and GPU.
- Sub Bus (16/8-bit) → Connects to the rest of the chips and I/O. This bus is bridged by the Bus Interface Unit, which also enables access to special ports of the GPU and SPU.
- 32-bit address bus: Up to 4 GB of physical memory (i.e. RAM, memory-mapped I/O, etc) can be accessed.
- 5-stage pipeline: Up to five instructions can be executed simultaneously (a detailed explanation can be found in a previous article).
- 4 KB instruction cache and 1 KB of data cache: The data cache also works as Scratchpad (fast RAM), meaning that it can have other uses apart from behaving as L1 cache. Instruction cache can be ‘isolated’ instead, allowing the program to manipulate it directly.
- For some reason, the original CW33300 contained 2 KB of data cache instead.
To do something meaningful, Sony provided 2 MB of RAM for general-purpose use. Curiously enough, they fitted External Data Out (EDO) chips on the motherboard. These are slightly more efficient than typical DRAM, obtaining lower latency.
Taking over the CPU
At some point, any subsystem (graphics, audio or CD) will require large chunks of data at a fast rate. However, the CPU will not always be able to keep up with the demand.
For this reason, the CD-ROM Controller, MDEC, GPU, SPU and the Parallel port have access to an exclusive DMA controller whenever they require it. DMA takes control of the main bus and performs a data transfer. The resulting rate is a lot faster than relying on the CPU, though the latter is still needed to set up a DMA transfer.