Aim: To model synchronous Mod-4 Up Counter using Verilog with JK flip-flop , verifying through simulation and observe RTL structure

Apparatus Required: Xilinx Vivado

Theory: A Mod-4 Counter (Modulo-4) cycles through four distinct states: 00 —> 01 —> 10—> 11 and then resets back to $00$. Since 2^n = 4, we require exactly two JK flip-flops (n=2). In a synchronous counter, the clock input of all flip-flops is connected to a common clock signal, ensuring all outputs change state simultaneously. The logic for a Mod-4 Up Counter is: • FF0: Toggles on every clock pulse (J_0 = 1, K_0 = 1). • FF1: Toggles only when Q0 is high (J_1 = Q_0, K_1 = Q_0).

Verilog Code:

// JK Flip-Flop Module
module jk_ff (
    input j, k, clk, reset,
    output reg q
);
    always @(posedge clk or posedge reset) begin
        if (reset)
            q <= 1'b0;
        else begin
            case ({j, k})
                2'b00: q <= q;    // Hold
                2'b01: q <= 1'b0; // Reset
                2'b10: q <= 1'b1; // Set
                2'b11: q <= ~q;   // Toggle
            endcase
        end
    end
endmodule

// Mod-4 Synchronous Up Counter
module mod4_counter (
    input clk, reset,
    output [1:0] q
);
    // Connection wires for J and K inputs
    wire j1, k1;

    // Logic for Mod-4: 
    // FF0 (LSB) always toggles: J0=1, K0=1
    // FF1 (MSB) toggles when Q0 is 1: J1=Q0, K1=Q0
    assign j1 = q[0];
    assign k1 = q[0];

    // Instantiating the two JK Flip-Flops
    jk_ff ff0 (.j(1'b1), .k(1'b1), .clk(clk), .reset(reset), .q(q[0]));
    jk_ff ff1 (.j(j1),   .k(k1),   .clk(clk), .reset(reset), .q(q[1]));

endmodule

Test Bench:

module tb_mod4_counter;
    reg clk;
    reg reset;
    wire [1:0] q;

    // Instantiate the Unit Under Test (UUT)
    mod4_counter uut (
        .clk(clk), 
        .reset(reset), 
        .q(q)
    );

    // Clock generation: 10ns period
    always #5 clk = ~clk;

    initial begin
        // Initialize inputs
        clk = 0;
        reset = 1;

        // Apply reset for 20ns
        #20 reset = 0;
        
        // Let it run for 100ns to see multiple cycles
        #100 $finish;
    end
    
    initial begin
        $monitor("Time=%0t | Reset=%b | Count=%d (%b)", $time, reset, q, q);
    end
endmodule

Conclusion: The Mod-4 Synchronous Up Counter was designed and simulated using Verilog HDL. By using two JK flip-flops and connecting the toggle logic of the second flip-flop to the output of the first, a clean transition through states 0, 1, 2, 3 was achieved. The simulation results verify that the counter resets correctly and operates synchronously with the clock, fulfilling the experiment's aim.