make
?
make
is an automation program that optimizes terminal processes by having a “script” of commands to be executed, which are predefined in the mandatory Makefile
file.target
), preventing mistakes caused by lack of attention.The Makefile has its writing rules, just like standard languages such as C, C++, Python...
Therefore, it has an expected writing pattern.
It has basic elements that can relate to each other, generating the “way make
will understand.”
/
tells make
to continue reading on the next line, equivalent to \\n
@
hidden command: executes the entire command line but does not show the command itself in the terminal
$
accesses the value of a variable declared inside the Makefile
$$
accesses the value of a variable declared in the terminal environment, not inside the Makefile
<name>:
declares a command <name>
, which after :
will be interpreted as an “executable,” meaning that when you run make <name>
, it will execute <name>
/target/
comes after <name>:
and serves as identification of what make
will look for. For example, setting an automation rule like: automation: main.c
make
has three possible scenarios:
<automation>
<automation>
execution:
<automation>
again=
is like declaring a variable... e.g., int i == 'i='
.PHONY
defines a command by itself, meaning a command without any target, executed simply by passing its own <name>
Example:
makefile
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.PHONY: first_make
first_make:
clear
Meaning make
will always execute first_make
regardless of target checks.