SR Flip Flop

module sr_ff(
    input clk,
    input S, R,
    output reg Q
);
initial Q=0;
always @(posedge clk)
begin
    case ({S, R})
        2'b00: Q <= Q;      // Hold
        2'b01: Q <= 0;      // Reset
        2'b10: Q <= 1;      // Set
        2'b11: Q <= 1'bx;   // Invalid
    endcase
end

endmodule

Test Bench

module sr_ff_tb;

reg clk, S, R;
wire Q;

sr_ff uut(.clk(clk), .S(S), .R(R), .Q(Q));

// Clock generation
always #5 clk = ~clk;

initial begin
    $monitor("S=%b,R=%b | Q=%b",S,R,Q);
    clk = 1;
    
    S=0; R=0; #10;
    S=0; R=1; #10;
    S=1; R=0; #10;
    S=1; R=1; #10;

    $finish;
end

endmodule

D Flip-Flop

module d_ff(
    input clk,
    input D,
    output reg Q
);

always @(posedge clk)
begin
    Q <= D;
end

endmodule

Test Bench

module d_ff_tb;

reg clk, D;
wire Q;

d_ff uut(.clk(clk), .D(D), .Q(Q));

always #5 clk = ~clk;

initial begin
    clk = 0;
    
    D=0; #10;
    D=1; #10;
    D=0; #10;
    D=1; #10;

    $finish;
end

endmodule

JK Flip Flop

module jk_ff(
    input clk,
    input J, K,
    output reg Q
);

always @(posedge clk)
begin
    case ({J, K})
        2'b00: Q <= Q;       // Hold
        2'b01: Q <= 0;       // Reset
        2'b10: Q <= 1;       // Set
        2'b11: Q <= ~Q;      // Toggle
    endcase
end

endmodule

Test Bench

module jk_ff_tb;

reg clk, J, K;
wire Q;

jk_ff uut(.clk(clk), .J(J), .K(K), .Q(Q));

always #5 clk = ~clk;

initial begin
    clk = 0;

    J=0; K=0; #10;
    J=0; K=1; #10;
    J=1; K=0; #10;
    J=1; K=1; #20;

    $finish;
end

endmodule

T Flip-Flop

module t_ff(
    input clk,
    input T,
    output reg Q
);

always @(posedge clk)
begin
    if (T == 1)
        Q <= ~Q;
    else
        Q <= Q;
end

endmodule

Test Bench

module t_ff_tb;

reg clk, T;
wire Q;

t_ff uut(.clk(clk), .T(T), .Q(Q));

always #5 clk = ~clk;

initial begin
    clk = 0;

    T=0; #10;
    T=1; #20;
    T=0; #10;
    T=1; #20;

    $finish;
end

endmodule

Universal Shift Register

module universal_shift_reg (
    input wire clk,
    input wire reset,        // Asynchronous active-high reset
    input wire [1:0] mode,   // 2-bit operation selector
    input wire [3:0] par_in, // 4-bit parallel data input
    input wire s_in_R,       // Serial input for Shift Right (enters at MSB)
    input wire s_in_L,       // Serial input for Shift Left (enters at LSB)
    output reg [3:0] Q       // 4-bit parallel output
);

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            Q <= 4'b0000;
        end else begin
            case (mode)
                2'b00: Q <= Q;                        // Hold
                2'b01: Q <= {s_in_R, Q[3:1]};         // Shift Right
                2'b10: Q <= {Q[2:0], s_in_L};         // Shift Left
                2'b11: Q <= par_in;                   // Parallel Load
                default: Q <= Q;                      // Default safety catch
            endcase
        end
    end

endmodule

Test Bench

module universal_shift_reg_tb;

// Inputs
reg clk;
reg reset;
reg [1:0] mode;
reg [3:0] par_in;
reg s_in_R;
reg s_in_L;

// Output
wire [3:0] Q;

// Instantiate DUT
universal_shift_reg uut (
    .clk(clk),
    .reset(reset),
    .mode(mode),
    .par_in(par_in),
    .s_in_R(s_in_R),
    .s_in_L(s_in_L),
    .Q(Q)
);

// Clock generation
always #5 clk = ~clk;

initial begin
    // Initialize
    clk = 0;
    reset = 1;
    mode = 2'b00;
    par_in = 4'b0000;
    s_in_R = 0;
    s_in_L = 0;

    // Monitor
    $monitor("Time=%0t | reset=%b mode=%b par_in=%b sR=%b sL=%b | Q=%b",
              $time, reset, mode, par_in, s_in_R, s_in_L, Q);

    // Apply reset
    #10 reset = 0;

    // -------------------------
    // Parallel Load
    // -------------------------
    mode = 2'b11;
    par_in = 4'b1011;
    #10;

    // -------------------------
    // Hold
    // -------------------------
    mode = 2'b00;
    #10;

    // -------------------------
    // Shift Right
    // -------------------------
    mode = 2'b01;
    s_in_R = 1; #10;
    s_in_R = 0; #10;

    // -------------------------
    // Shift Left
    // -------------------------
    mode = 2'b10;
    s_in_L = 1; #10;
    s_in_L = 0; #10;

    // -------------------------
    // Another Parallel Load
    // -------------------------
    mode = 2'b11;
    par_in = 4'b1100;
    #10;

    // Finish simulation
    $finish;
end

endmodule