Non Overlap Code

module seq_det_1011_non_overlap (
    input wire clk,
    input wire reset,
    input wire in,
    output wire out
);

    // Define states using localparam for readability
    localparam S0 = 2'b00; // Got nothing
    localparam S1 = 2'b01; // Got 1
    localparam S2 = 2'b10; // Got 10
    localparam S3 = 2'b11; // Got 101

    reg [1:0] state, next_state;

    // 1. Sequential Logic: State Register
    always @(posedge clk or posedge reset) begin
        if (reset)
            state <= S0;
        else
            state <= next_state;
    end

    // 2. Combinational Logic: Next State Routing
    always @(*) begin
        case (state)
            S0: next_state = (in) ? S1 : S0;
            S1: next_state = (in) ? S1 : S2;
            S2: next_state = (in) ? S3 : S0;
            S3: next_state = (in) ? S0 : S2; // NON-OVERLAPPING: Returns to S0 on success
            default: next_state = S0;
        endcase
    end

    // 3. Combinational Logic: Mealy Output
    // Output is HIGH only when we are in S3 (have "101") and the current input is '1'
    assign out = (state == S3 && in == 1'b1) ? 1'b1 : 1'b0;

endmodule

Test Bench

module tb_seq_detectors();

    reg clk;
    reg reset;
    reg in;

    wire out_non_overlap;
    wire out_overlap;

    // Instantiate Non-Overlapping Detector
    seq_det_1011_non_overlap uut_non_ov (
        .clk(clk), .reset(reset), .in(in), .out(out_non_overlap)
    );

    // Instantiate Overlapping Detector
    seq_det_1011_overlap uut_ov (
        .clk(clk), .reset(reset), .in(in), .out(out_overlap)
    );

    // Clock Generation (10ns period)
    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end

    // Test Sequence Array
    // We will feed: 0, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0
    reg [11:0] test_sequence = 12'b010110110110; 
    integer i;

    initial begin
        // Setup waveform dumping
        $dumpfile("seq_detect.vcd");
        $dumpvars(0, tb_seq_detectors);

        // 1. Initialize and Reset
        in = 0;
        reset = 1;
        #12 reset = 0; // Release reset just after a clock edge

        // 2. Feed the bitstream sequentially
        // We shift the test_sequence bit by bit from MSB to LSB
        for (i = 11; i >= 0; i = i - 1) begin
            in = test_sequence[i];
            #10; // Wait for one full clock cycle per bit
        end

        // Wait a moment before finishing
        #20;
        $finish;
    end

    // Console Output Monitor
    initial begin
        $display("Time | In | State(Non-Ov) | State(Ov) | Out(Non-Ov) | Out(Ov)");
        $display("---------------------------------------------------------------");
        // We use $strobe instead of $monitor here so it prints the values at the very END of the time step, 
        // ensuring we capture the combinational Mealy output correctly after the state settles.
        forever #10 $strobe("%0t   | %b  |      %b      |     %b    |      %b      |    %b", 
                 $time, in, uut_non_ov.state, uut_ov.state, out_non_overlap, out_overlap);
    end

endmodule