1. Should we have 1024 general-purpose registers in the ISA? No.

• Register assess time may take longer, thus increasing the clock cycle time.
• Procedure call overhead will increase since too many registers to save and restore.
• Context switching cost will increase.
• Instruction length will increase, 32 bit is no longer sufficient.

1. Should we use Compare and Branch or Condition-Code-based branches? Compare and Branch.

• RISC-V, as a modern RISC ISA, uses compare and branch instructions (e.g., beq rs1, rs2, label), avoiding global condition codes.
• Avoiding condition codes simplifies hardware design, especially for pipelined and out-of-order execution, aligning with RISC philosophy.
• Condition codes introduce an implicit state, which can create dependencies and complicate instruction scheduling and high-performance implementations. (CISC)

1. Should we support fast procedure calls with a single instruction? Yes.

• Instructions like JAL (Jump and Link) and JALR (Jump and Link Register) in RISC-V combine the jump to the procedure and saving the return address into a single instruction.
• This improves efficiency by reducing instruction count for a fundamental operation.
• It simplifies compiler design for implementing procedure calls.
• May require dedicated hardware or limit flexibility.

1. Should we support 3-operand or 4-operand instruction formats? Primarily 3-operand, with exceptions for highly beneficial special instructions.

• Most RISC-V arithmetic and logical instructions use a 3-operand format (e.g., add rd, rs1, rs2).
• This format offers a good balance between expressiveness and simplicity, facilitating regular instruction decoding and hardware design.
• While 4-operand formats can exist for specialized instructions like Fused Multiply-Add (FMA), making it a general format would increase instruction length and hardware complexity.
• A general 4-operand format might also disrupt the regularity of the instruction set.