Data Path: manages data flow

Control: manages instruction flow

The separation makes the design more modular, easier to design, reusable, and scalable.

RV32I data Path and Control

Focus on

Instruction Execution

Single Cycle: All operations —— IF, ID, EX, MEM, WB —— occur within one cycle. This requirement leads to a longer clock cycle to accommodate the slowest instruction, which often results in a lower clock frequency. The complexity of a given instruction can influence the cycle time.

→ leads to the revolution of RISC architecture

Multi-cycle: Instructions are broken down into multiple steps, each taking one clock cycle. This allows for a shorter clock cycle, higher clock frequency, and more efficient use of hardware resources.

时钟周期需要自己设置

CISC machines: Lower instruction count, higher CPI, longer cycle time

RISC machines: higher instruction count, lower CPI, shorter cycle time

• x86 is CISC ISA, but micro-operations are RISC.