Objective: To design Carry Look-Ahead Adder using Verilog RTL and verify through simulate functionality.

Tool Used: Xilinx Vivado

Theory:

A Carry Look Ahead Adder (CLA) is a fast adder used in digital systems to overcome the delay caused by carry propagation in ripple carry adders. Instead of waiting for each carry to propagate sequentially, the CLA computes carry signals in advance using generate (G) and propagate (P) functions.

For each bit,

• Generate: G=A⋅B
• Propagate: P=A⊕B

Using these, carry outputs are calculated in parallel, significantly reducing computation time. The sum is then obtained using the propagate and carry values.

The circuitry of a CLA includes AND, OR, and XOR gates, along with combinational logic to generate carry signals quickly. This parallel carry computation makes CLA much faster compared to conventional adders.

// Half Adder Module
module halfadder (
    output S, C,
    input x, y
);
    xor (S, x, y);
    and (C, x, y);
endmodule

// Carry Generator Module
module carrygenerator (
    input cin, 
    input p0, p1, p2, p3, 
    input g0, g1, g2, g3,
    output c0, c1, c2, c3, c4
);

    assign c0 = cin;
    assign c1 = g0 | (p0 & cin);
    assign c2 = g1 | (p1 & g0) | (p1 & p0 & cin);
    assign c3 = g2 | (p2 & g1) | (p2 & p1 & g0) | (p2 & p1 & p0 & cin);
    assign c4 = g3 | (p3 & g2) | (p3 & p2 & g1) | 
                (p3 & p2 & p1 & g0) | (p3 & p2 & p1 & p0 & cin);

endmodule

// 4-bit Carry Lookahead Adder
module CLA_Adder (
    input [3:0] a, b,
    input cin,
    output [3:0] sum,
    output cout
);

    wire p0, p1, p2, p3;
    wire g0, g1, g2, g3;
    wire c0, c1, c2, c3, c4;

    // Half Adders to generate propagate and generate signals
    halfadder HA0(p0, g0, a[0], b[0]);
    halfadder HA1(p1, g1, a[1], b[1]);
    halfadder HA2(p2, g2, a[2], b[2]);
    halfadder HA3(p3, g3, a[3], b[3]);

    // Carry Generator
    carrygenerator CG(cin, p0, p1, p2, p3, g0, g1, g2, g3, c0, c1, c2, c3, c4);

    // Sum calculation
    assign sum[0] = p0 ^ c0;
    assign sum[1] = p1 ^ c1;
    assign sum[2] = p2 ^ c2;
    assign sum[3] = p3 ^ c3;

    assign cout = c4;

endmodule

Test Bench

`timescale 1ns/1ps

module CLA_Adder_tb;

    reg [3:0] a, b;
    reg cin;
    wire [3:0] sum;
    wire cout;

    // Instantiate the DUT (Device Under Test)
    CLA_Adder uut (
        .a(a),
        .b(b),
        .cin(cin),
        .sum(sum),
        .cout(cout)
    );

    initial begin
        // Monitor values
        $monitor("Time=%0t | a=%b b=%b cin=%b | sum=%b cout=%b", 
                  $time, a, b, cin, sum, cout);

        // Test cases
        a=4'b0000; b=4'b0000; cin=0; #10;
        a=4'b0001; b=4'b0010; cin=0; #10;
        a=4'b0101; b=4'b0011; cin=0; #10;
        a=4'b1111; b=4'b0001; cin=0; #10;
        a=4'b1010; b=4'b0101; cin=1; #10;
        a=4'b1111; b=4'b1111; cin=1; #10;

        $finish;
    end

endmodule

Conclusion: The Carry Look Ahead Adder was designed and simulated, showing faster carry computation compared to ripple adders. The use of generate and propagate signals improved performance. Simulation in Xilinx Vivado confirmed correct sum and carry outputs.