Objective: To design Asynchronous Up & Down Counter in Verilog; simulate functionality.

Tool Used: Xilinx Vivado

Theory:

An asynchronous (ripple) counter is a sequential circuit where flip-flops are triggered one after another, not simultaneously by a common clock. In this design, a MOD-6 counter is implemented, which cycles through 6 states (0 to 5) and then resets.

The circuit uses T flip-flops, where the output toggles when T = 1. The first flip-flop is driven by the external clock, while the remaining flip-flops are triggered by the output of the previous stage, forming a ripple effect.

To limit the count to 6 states, combinational logic using NAND and OR gates is used to detect the invalid state (binary 110). When this state occurs, a reset signal is generated, forcing the counter back to 000, thus achieving MOD-6 operation.

For the up counter, each flip-flop is triggered by the normal output of the previous stage, whereas for the down counter, inverted outputs are used to achieve reverse counting.

Up Counter

module mod6_up_async (
    input clk,
    input rst,
    output reg [2:0] Q
);

always @(posedge clk or posedge rst) begin
    if (rst)
        Q <= 3'b000;
    else begin
        if (Q == 3'b101)   // 5
            Q <= 3'b000;
        else
            Q <= Q + 1;
    end
end

endmodule

Down Counter

module mod6_down_async (
    input clk,
    input rst,
    output reg [2:0] Q
);

always @(posedge clk or posedge rst) begin
    if (rst)
        Q <= 3'b101;   // start from 5
    else begin
        if (Q == 3'b000)
            Q <= 3'b101;
        else
            Q <= Q - 1;
    end
end

endmodule

Test Bench

module tb_mod6_counters;

reg clk;
reg rst;

wire [2:0] up_Q;
wire [2:0] down_Q;

// Instantiate UP counter
mod6_up_async up_counter (
    .clk(clk),
    .rst(rst),
    .Q(up_Q)
);

// Instantiate DOWN counter
mod6_down_async down_counter (
    .clk(clk),
    .rst(rst),
    .Q(down_Q)
);

// Clock generation
always #5 clk = ~clk;

initial begin
    clk = 0;
    rst = 1;

    // Apply reset
    #10 rst = 0;

    // Run simulation
    #100;

    $finish;
end

// Monitor outputs
initial begin
    $monitor("Time=%0t | UP=%b | DOWN=%b", $time, up_Q, down_Q);
end

endmodule

Conclusion: The MOD-6 asynchronous up and down counters were implemented using T flip-flops and verified successfully. The counter correctly cycled through six states with proper reset logic. Simulation in Xilinx Vivado confirmed accurate counting in both directions.