RTL & Digital Circuit Learner
λμ§νΈ νλ‘ μ€κ³ λ° κ²μ¦μ λν μ΄ν΄λ₯Ό λ°νμΌλ‘,
λ λμ νλ‘ μ€κ³ μ λ¬Έκ°κ° λκΈ° μν΄ λμμμ΄ λ°°μ°κ³ λμ νκ³ μμ΅λλ€!
π± Phone : 010-2431-5589
π§ E-mail : jiyun.dev00@gmail.com
π GitHub : github.com/jiyun-han
π PROFILE
κ²½λ ₯ (Career)
νλ ₯ (Education)
2019.03 ~ 2025.08μμ€λνκ΅ μ 기곡νλΆ(μ κΈ°μ 보μ 곡) μ‘Έμ
(λΆμ 곡 : μ°¨μΈλλ°λ체νκ³Ό)
μκ²©μ¦ (Certificate) / μ΄ν
`2024.08` OPIc(μμ΄) - IM1
`2020.05` μ»΄ν¨ν°νμ©λ₯λ ₯ 1κΈ
`2019.01` 1μ’
λ³΄ν΅ μ΄μ λ©΄ν
μμλ΄μ (be awarded)
`2025.01` POLARIS SIF 2025 μν λΆλ¬Έ_μ₯λ €μ
`2024.11` AIλ°λ체 νλ‘μ€κ³ κ²½μ§λν_Cadence Award
`2024.07` μμ€λνκ΅ κ³΅κ³Όλν - μμ€κ³΅νμ_κΈμ
π SKILL
π₯οΈ Hardware Design Tools
(EDA Tools)
- :com-github-corna-vivado: Xilinx - Vivado
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Lv.8
- :intel-quartus-prime-pro: Intel(Altera) - Quartus
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Lv.6
- :questasim: Mento Graphics - Questa
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Lv.5
- :cadence: Cadence - Virtuoso
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Lv.6
- :cadence: Cadence - Xcelium
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Lv.3
π₯οΈ Programming &
HDL Languages
- :verilog--vhdl: Verilog-HDL
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Lv.8
- :python-logo-notext-svg: Python
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Lv.7
- :verilog--vhdl: VHDL
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Lv.6
- :c: C
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Lv.5
- :verilog--vhdl: SystemVerilog
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Lv.4
π PROJECT
μ 곡 νλ‘μ νΈ (Academic Projects)
νλ‘μ νΈ