Location: Leuven, Belgium (hybrid) — monthly travel to Belgium

Job Description

We are looking for an ASIC Team Lead to spearhead Belfort’s transition from FPGA acceleration to custom silicon. You will lead the efforts of converting our unique cryptographic acceleration technology into an ASIC, assembling the required team.

Our cryptographic team has strong hardware design expertise, and we have a competitive FPGA design already available. We now look to complement the team with a senior ASIC leader who can drive the architecture, design, and implementation roadmap toward silicon.

In this role, you will initiate and coordinate Belfort’s ASIC program, from feasibility and design methodology setup, through RTL-to-GDSII flows, to early test-chip planning. You will be a key technical leader shaping the future of Belfort’s acceleration roadmap.

Responsibilities

ASIC Conversion Leadership

• Drive the adaptation of Belfort’s FPGA-based cryptographic accelerators into ASIC-ready architectures
• Define the ASIC design methodology, toolchains, and verification environments
• Collaborate with FPGA and cryptography teams to identify design modifications for ASIC feasibility and performance
• Assemble a competitive team

Architecture & Design

• Lead RTL development and guide micro-architectural trade-offs for area, power, and performance optimization
• Evaluate technology nodes and process options to ensure scalability and competitiveness
• Define IP strategy for critical system blocks such as interconnects, memory, and accelerators

Verification & Validation

• Establish ASIC verification methodologies (UVM/SystemVerilog, DFT, formal verification)
• Plan and coordinate functional and system-level validation for first silicon