Location: Leuven, Belgium (hybrid) — monthly travel to Belgium

Job Description

We are seeking an ASIC Design Architect to lead the technical definition and realization of Belfort’s first custom silicon. Building on our proven FPGA-based cryptographic accelerators, you will architect the transition to ASIC, defining the micro-architecture, methodology, and design strategy that will shape Belfort’s long-term silicon roadmap, in addition to assembling the required team.

This role, you will initiate and coordinate Belfort’s ASIC program, with a focus on architecture exploration, RTL-level design tradeoffs, and methodology definition. You will collaborate closely with our cryptography and FPGA design teams to translate innovative hardware acceleration into ASIC-ready implementations, and engage with external partners to ensure successful tape-out.

You will be a key technical leader shaping the future of Belfort’s acceleration roadmap.

Responsibilities

Architecture Definition

• Define ASIC architecture for Belfort’s cryptographic acceleration technology, including top-level partitioning, interconnect, and memory hierarchy.
• Explore and evaluate technology nodes, process options, and design trade-offs for area, power, and performance optimization.
• Establish IP integration strategy for critical components (interconnect, memory, accelerators).

ASIC Conversion Leadership

• Drive the adaptation of Belfort’s FPGA-based cryptographic accelerators into ASIC-ready architectures
• Define the ASIC design methodology, toolchains, and verification environments
• Collaborate with FPGA and cryptography teams to identify design modifications for ASIC feasibility and performance
• Assemble a competitive team

Verification & Validation

• Establish ASIC verification methodologies (UVM/SystemVerilog, DFT, formal verification)