2:1 Mux

module mux_2to1(
    input I0, I1,
    input S,
    output Y
);

assign Y = (S) ? I1 : I0;

endmodule

Test Bench

module mux_2to1_tb;

reg I0, I1, S;
wire Y;

mux_2to1 uut (.I0(I0), .I1(I1), .S(S), .Y(Y));

initial begin
    $monitor("I0=%b I1=%b S=%b | Y=%b", I0, I1, S, Y);

    I0=0; I1=1; S=0; #10;
    I0=0; I1=1; S=1; #10;
    I0=1; I1=0; S=0; #10;
    I0=1; I1=0; S=1; #10;

    $finish;
end

endmodule

4:1 Mux

module mux_4to1(
    input I0, I1, I2, I3,
    input [1:0] S,
    output reg Y
);

always @(*) begin
    case(S)
        2'b00: Y = I0;
        2'b01: Y = I1;
        2'b10: Y = I2;
        2'b11: Y = I3;
    endcase
end

endmodule

Test Bench

module mux_4to1_tb;

reg I0, I1, I2, I3;
reg [1:0] S;
wire Y;

mux_4to1 uut (.I0(I0), .I1(I1), .I2(I2), .I3(I3), .S(S), .Y(Y));

initial begin
    $monitor("S=%b | Y=%b", S, Y);

    I0=0; I1=1; I2=0; I3=1;

    S=2'b00; #10;
    S=2'b01; #10;
    S=2'b10; #10;
    S=2'b11; #10;

    $finish;
end

endmodule

4:1 using 2:1 Mux

module mux_4to1_using_2to1(
    input I0, I1, I2, I3,
    input [1:0] S,
    output Y
);

wire w1, w2;

// First stage
mux_2to1 m1 (.I0(I0), .I1(I1), .S(S[0]), .Y(w1));
mux_2to1 m2 (.I0(I2), .I1(I3), .S(S[0]), .Y(w2));

// Second stage
mux_2to1 m3 (.I0(w1), .I1(w2), .S(S[1]), .Y(Y));

endmodule

Test Bench

module mux_4to1_using_2to1_tb;

reg I0, I1, I2, I3;
reg [1:0] S;
wire Y;

mux_4to1_using_2to1 uut (
    .I0(I0), .I1(I1), .I2(I2), .I3(I3),
    .S(S), .Y(Y)
);

initial begin
    $monitor("S=%b | Y=%b", S, Y);

    I0=0; I1=1; I2=0; I3=1;

    S=2'b00; #10;
    S=2'b01; #10;
    S=2'b10; #10;
    S=2'b11; #10;

    $finish;
end

endmodule